As is well known in the art, during the production of monolithic memory devices from silicon wafers, some of the memory storage cells can become defective and unreliable. The defective cells can be the result of a number of causes, such as impurities introduced in the process of manufacturing the monolithic memory device from the silicon wafer, or localized imperfections in the silicon substrate itself.
Often, while some memory cells are defective, many other cells on the same memory chip are not defective, and will work reliably and accurately. In addition, it is often the case that the defective cells are localized and confined to particular outputs from the memory device. The remaining, nondefective outputs can be relied upon to provide a consistent and accurate representation of the information in the storage cell.
Techniques have been developed for salvaging the non-defective portions of defective asynchronous memory technologies (e.g., DRAM). Asynchronous memory technologies are relatively slow devices that operate in response to control signals generated by a memory controller, rather than in response to the system clock. The control signals allow the asynchronous memory device to operate at a speed that is much slower than the system clock, and that ensures reliable read and write memory operations.
Synchronous memory devices such as SDRAM, on the other hand, are much faster devices that operate on the system clock. SDRAM is an improvement over prior memory technologies principally because SDRAM is capable of synchronizing itself with the microprocessor's clock. This synchronization can eliminate the time delays and wait states often necessary with prior memory technologies (e.g., DRAM), and it also allows for fast consecutive read and write capability.
However, no attempts have been made to salvage non-defective portions of synchronous memory. Some people skilled in the art may believe that the use of techniques for salvaging defective memory devices would not work with higher-speed synchronous memory devices such as SDRAM because they operate at much higher speeds than previous memory devices, such as asynchronous DRAM. For SDRAM, it may be believed that the rate at which the clock input cycles and the load on the device driving the inputs (e.g., the clock and the address) to the SDRAM devices would make reliable input transitions unattainable.
The present invention addresses the problem of salvaging partially defective synchronous memory devices. In one embodiment of the present invention, multiple partially defective SDRAM components are configured to provide a reliable and nondefective memory module. Such an embodiment takes advantage of the manner in which defective cells are localized on each memory chip, and combines multiple memory chips to provide a memory bus that is of the desired width and granularity. In addition, it is possible with such an embodiment to provide a computer system in which the main memory is synchronized with the system clock, and is constructed, at least in part, from partially defective memory chips.
The nature of the present invention as well as other embodiments of the present invention may be more clearly understood by reference to the following detailed description of the invention, to the appended claims, and to the several drawings herein.